A low drop-out (LDO) regulator is a linear regulator which utilizes a transistor or FET to generate a regulated output voltage with very low differential between the input voltage and the output voltage. In battery powered devices, it is common to have a switching regulator such as a buck regulator between the battery and a LDO regulator. This circuit arrangement combines the efficiency of a switching regulator and the fast response of a LDO regulator. In order to maximize the efficiency, it is common to have the output of the switching regulator be very close to the desired regulated voltage. This creates a problem for the drive of the pass transistor of the LDO regulator, typically a PMOS transistor, because the low voltage input will limit the maximum input voltage Vgs that can be applied to the gate of the pass transistor.
FIG. 1 illustrates a known LDO regulator generally shown as 100. A positive output terminal of a reference voltage source 102 is connected to input 104 of operational amplifier 108, the other terminal being coupled to ground via line 106. A second input 105 to the operational amplifier 108 is coupled to ground via resistor 110 and to the output voltage via resistor 112. The output voltage is generated by pass transistor 118 from voltage source (VIN_PWR) 120, which can be the output of the buck regulator, for example (not shown). The back gate of transistor 118 is connected to voltage source 120. The output voltage is generated across output resistor 136 and an output capacitor 138. The equation giving the maximum amount of Vgs that can be applied to the PMOS device 118 is given by equation 1:Vgs.max=VIN_PWR−Vamp.min  equation (1) 
where Vamp.min=minimum output voltage of operational amplifier
As seen from equation (1), Vgs will depend on the output voltage swing of the operational amplifier which can further reduce a possible gate drive that can be applied to the MOS output device. For example, if the regulated input voltage on pin 120 is 1.5 V, and the operational amplifier has a minimum output voltage of 0.3 V, a weak transistor having a Vt of one volt, in the worst case, we have a maximum drive of only 0.2 V.
A known solution for this problem is shown in FIG. 2 generally as 200. The circuit of FIG. 2 is similar to the circuit of FIG. 1 and similar components have similar reference numerals. In FIG. 2, the back gate of transistor 218 is not connected directly to the voltage source 220. Instead, it is connected to the input voltage source 220 by Schottky diode 239. The junction of Schottky diode 239 and back gate 218 is coupled via line 240 to NMOS transistor 248, the source of which is coupled to ground via line 250. The gate of transistor 248 is coupled via line 246 to diode connected NMOS transistor 244 which functions as a current mirror to mirror a portion of current flowing through transistor 218 as sampled by NMOS sampling transistor 216. Thus, as the output current increases, the current through the Schottky diode increases which applies a lower voltage to the back gate of transistor 218 which lowers the Vt of the transistor.
One problem with the solution is the need for the Schottky diode which is not available in many semiconductor processes. In some processes the Schottky diodes formed on the integrated circuits have voltage drops that are high enough to forward bias the source-back gate junction. It is critical that the amount of forward bias applied is precisely controlled because too much can mean that the source-back gate junction starts injecting a considerable amount of carriers and the circuit latches up. Too little will not achieve significant lowering of the Vt of the pass transistor. Utilization of discrete components in addition to the integrated circuit is highly undesirable because it increases the size required for the circuit as well as the cost and generally lowers the reliability.
According, there is a need for a circuit that can achieve the objective of lowering the Vt of the pass transistor which can be on an integrated circuit and does not require additional processes in the formation of the integrated circuit.